1. Field of the Invention
The present invention relates generally to a non-volatile semiconductor memory, and more specifically, the to a Flash type Electrically Erasable and Programmable Read Only Memory (Flash EEPROM) capable of substantially simultaneously erasing all data stored therein using an electrical signal.
2. Description of the Prior Art
An Erasable and Programmable Read Only Memory (EPROM) has been used in, for example, microcomputers as a program memory. The EPROM needs ultraviolet light To erase all data stored therein. Recently, the EPROM is being replaced with the Flash EEPROM because there is no need in the Flash EEPROM system to use ultraviolet light To erase the data stored therein. The Flash EEPROM uses an electrical signal as a substitute for the ultraviolet light of the EPROM.
FIG. 1 is a cross-sectional view showing a memory cell of a conventional Flash EEPROM.
In the conventional Flash EEPROM, source region 10 and drain region 11 are formed in P-type silicon semiconductor substrate 12. Floating gate 13 is formed over the channel region between source region 10 and drain region 11, on first gate insulating film 14. Control gate 15 is formed over the floating gate 13 and on second gate insulating film 16. The floating gate 13 is electrically isolated from other electrodes by the first and the second insulating films 16 and 14.
FIG. 2 is a circuit diagram of a part of the Flash EEPROM.
A plurality of memory cells 20a, 20b, 20c and 20d are arranged as shown in FIG. 2. Drain electrodes of the memory cells 20a and 20c are connected to one of the bit lines 21a, and drain electrodes of the memory cells 20b and 20d are connected to another bit line 2lb. The bit lines 21a and 2lb are connected to sense amplifier 22. Bit lines 21a and 2lb are selected by MOS transistors 23a and 23b. Each of transistors 23a and 23b are inserted into one of the bit line 21a and 2lb respectively and gate electrodes of the transistors 23a and 23b are supplied with a part of an address signal. Control gates of the memory cells 20a and 20b are mutually connected and function as one of the word lines 24a. Similarly, control gates of the memory cells 20c and 20d are mutually connected and function as another one of the word lines 24b. Word lines 24a and 24b are supplied with the other part of the address signal.
Operation of the conventional Flash EEPROM is as follows.
When writing data to the cell, a high voltage such as 10 V is impressed on the control gate 15 and on the drain region 11, and grounded voltage is impressed on the source region 10. By doing this, electrons flow from source region 10 and are accelerated in the channel region. Then, a portion of the electrons become hot electrons and are injected into the floating gate 13 via the first gate insulating film 14. The total amount of electrons to be injected is determined by the potential of the floating gate 13.
Then, the threshold voltage Vth of the memory cell, which is controlled by the total amount of injected electrons, increases, and the presence or absence of the threshold voltage variation component .DELTA.Vth is made to correspond to data levels 1 or 0. Generally, it is desirable that the threshold voltage should shift greatly with a low impressed voltage and short writing time.
On the other hand, data erase is executed by emitting the injected electrons from the floating gate 13. For this purpose, a high voltage such as 10 V is impressed on the source region 10, and a grounded voltage is impressed on the control gate 15.
The characteristics of these injection and emission of electrons are determined by the potential difference between the floating gate 13 and the source region 10. Namely, if the potential difference is great, the velocity of the injection into the floating gate 13 or the emission from the floating gate 13 is rapid. The potential difference between the floating gate 13 and the source region 10 is determined by the voltage difference between the source region 10 and the control gate 15, and by the ratio of the capacitance Cs formed between the source region 10 and the floating gate 13 to the capacitance C1 formed between the floating gate 13 and the control gate 15. The potential difference between the floating gate 13 and the source region 10 is expressed as follows, taking the source region voltage as Vs and the floating gate voltage as Vfg. Capacitance C2 is the capacitance between the floating gate 13 and the channel region. EQU Vs-Vfg=(1-Cs/(Cs+C1+C2)) Vs+Qf/(Cs+C1+C2) (1)
Here, Qf is the charge stored in the floating gate.
Due to the electrons injected to the floating gate 13, the threshold voltage variation component .DELTA.Vth is also expressed as follows. EQU .DELTA.Vth=-Qf/C1 (2)
FIG. 3 shows erase characteristic curves of the conventional memory cell taking the initial value of Vth as 4 V.
When the conventional memory cells are used in a Flash EEPROM array, over-erasure becomes a problem. Namely, erase characteristics of the memory cells 20a, 20b, 20c and 20d are different from each other due to structural parameters of the memory cells, such as the dispersion of the channel width, length and concentration, the insulating (oxide) film thickness and the superimposed area of the control gate and the floating gate of the memory cells. That is to say, when one of the memory cells is sufficiently erased, another memory cell might have been already over-erased and its threshold voltage Vth falls below 0 V. Here, the case of desiring to detect OFF when Vth is above the voltage of the selected word line is studied. At this time, if cell 20a, for example, is in the over-erased state, and its threshold value is below 0 V, the current flows in the selected bit line even if the potential of non-selected word line 24a is 0 V. That is to say, it cannot be sensed that cell 20a is OFF. Therefore the memory itself becomes defective.
In order prevent this over-erasure, the design must be such that, at the point at which the cell in which erasure is slowest exceeds the maximum Vth (VthE) which can be sensed as erased, the cell in which erasure is fastest should not exceed the point of Vth=0.
The speed of erasure is greatly influenced by the structural parameters. Controlling randomness in these becomes increasingly difficult with cell miniaturization and the large capacity memories.
On the other hand, when considered from the circuit point of view, if VthE is set high, the risk of over-erasure will be reduced. However, the power source margin will deteriorate and, in particular, the cell current will decrease. Therefore, deterioration of access time can be predicted. Also, reduction of the power source voltage due to future device miniaturization cannot be accommodated.